1. Field of the Invention
The present invention relates generally to a method of making an LDMOS (Lateral Double-diffused Metal Oxide Semiconductor) transistor, and more particularly to a method of producing an LDMOS transistor using a tapered P-type region.
2. Description of the Related Art
Power semiconductor devices are currently being used in many applications. A commonly used high-voltage component for these circuits is the LDMOS transistor. The LDMOS transistor structure has been widely used in intelligent power applications. It has the advantages of process compatibility with VLSI process and is easily integrated with other processing.
For power devices, a specific "on" resistance and breakdown voltage are critical to device performance. The main objective of the design of the LDMOS device is to minimize "on" resistance, while still maintaining high breakdown voltages. However, these two electrical parameters tend to have conflicting requirements as far as processing variables such as epitaxial doping and thicknesses are concerned.
To this end, a double RESURF (REduced SURface Field) structure has been proposed. FIGS. 1(a) to 1(e) are schematic cross-sectional process flow diagrams illustrating the major steps in processing a double RESURF to fabricate LDMOS transistors in accordance with the conventional art.
Referring to FIG. 1(a), on a p-type silicon substrate 10, a p-type epitaxial layer 11 is formed, and then an n-type drift region 12 is formed on the p epitaxial layer 11 by ion implantation process. A p-type top layer 13 is formed into the n drift region 12 by an ion implanting using a mask pattern 101 as a mask and a drive-in process.
Then, a LOCOS (LOCal Oxidation) process for forming field oxides is carried out. Firstly, as shown in FIG. 1(b), a pad oxide layer 14 and a nitride pattern 102 are sequentially formed on the resultant structure after the mask pattern 101 is removed. Secondly, the opened pad oxide 14 is grown by oxidation process at high temperature of 1000 degree Celsius or more, and then a field oxide 15 is formed, as shown in FIG. 1(c). Then, the remaining pad oxide layer 14 is removed.
Referring to FIG. 1(d), a gate conductive layer 16 is formed. Then, an N+ source region 17 is formed in the exposed n drift region 12 by ion implanting, and N+ drain region 18 and P+ region are formed in the exposed p-type epitaxial layer 11, respectively.
Referring to FIG. 1(e), on the entire surface of resultant structure, an interlayer dielectric 19 is formed, and then opening process are carried out using a mask pattern 103 as an etching mask.
As described above, in this double RESURF structure the p top layer 13 is introduced in the n drift region 12. The p top layer 13 helps the n drift region 12 to be easily depleted even if the concentration of the n drift region 12 is set high enough to reduce the on-resistance. That is, the double depletion region are formed between the p epitaxial layer 11 and the n drift region 12 and between the n drift region 12 and the p top layer 13, respectively. As a result, the on-resistance is improved.
However, in the aforementioned double RESURF structure using the p top layer 13, the length of the drift region 12 is significantly increased since the p top layer 13 is formed by the sophisticated ion implanting and drive-in process of high temperature, thereby causing to increase the on-resistance of devices in the conventional method. Additionally, the conventional method has disadvantages in that it raises an out-diffusion of dopants in the drift region 12 and the p top layer 13 due to the high temperature oxidation for forming the field oxide 15.
Thus, what is needed is to develop double RESURF structure with improved p top layer to be able to fabricated without high temperature drive-in and oxidation processes causing the increasement of the drift region and out diffusion of dopant.
Ultimately, the conventional double RESURF LDMOS technologies are disadvantageous in that high breakdown voltage cannot coexist with low on-resistance.